Frequently, at least in the video signal processing arts, it is desired to generate a clock signal which is phase aligned to some reference signal. The approach that is typically implemented is to apply a master clock signal to a cascade arrangement of inverting amplifier. The output of each amplifer is delayed relative to the clock signal applied to its input connection due to the inherent processing delay of the amplifier. Thus the cascade connection provides, at respective amplifier connections, a plurality of clock signals each of which has a different phase delay relative to the original master clock signal. The respective clock signals are coupled in parallel to a multiplexing circuit which is conditioned by control circuitry to select a desired one of the clock signals. FIG. 5 shows such a circuit arrangement and is representative of apparatus disclosed in U.S. Pat. Nos. 4,498,342 and 4,814,879. The number of inverting amplifiers in the cascade arrangement is a function of the desired phase resolution. Consider for example that the master clock period is 70ns, and that the inherent delay of each inverting amplifier is one nanosecond. To provide clock signals with two nanosecond phase differences over one clock cycle requires 70 inverting amplifiers. Typically, however, a more coarse phase resolution is all that is needed. This can be provided with fewer inverting amplifiers in the cascade arrangement by slowing the response time of ones of the amplifiers. This is achieved by capacitively loading alternate ones of the amplifiers in the cascade arrangement. For example, in FIG. 5, the first, third, fifth and all odd numbered amplifiers include a capacitor load at their respective output connections. The intermediate (even numbered amplifiers) are not capacitively loaded. The reason for this is demonstrated in FIG. 1. FIGS. 1A-1F illustrate the signal waveforms present at for example the clock input and the first five inverting amplifier output connections respectively. FIGS. 1B, 1D and 1F represent (in exaggerated form) the output waveforms at the capacitively loaded interconnections. It is seen that the integrity of the original waveform (FIG. 1A) is significantly degraded at the output connections of the capacitively loaded stage (FIG. 1B). The degraded waveforms are substantially restored to conform to the original clock waveshape by virtue of the intervening amplifiers in the cascade arrangement. Note the assumption is made that the inverting amplifiers have relatively high voltage gain.
Assume that each inverting amplifier is formed with a common emitter or common source amplifier transistor, Tn, with a current source load device, Isource, as illustrated in FIG. 6A or alternatively formed by complementary transistors, Tp and Tn, as illustrated in FIG. 6B (FIGS. 6A and 6B each illustrate exemplary circuitry of two successive stages of a cascade arrangement of inverting amplifiers.) Knowing the amplifier and load parameters one can design a system as shown in FIG. 5 which will generate symmetrical waveforms as illustrated in FIG. 1.
The waveforms of FIGS. 1A-1E correspond to signals exhibited at nodes A-E in FIG. 5. In FIGS. 1B and 1D the dashed horizontal lines are meant to indicate the threshold potentials of the successive inverting amplifier stages (i.e., the minimum potential required to condition the common source amplifier tranistor, Tn, (FIG. 6A) into conduction). At the point in time, indicated by the vertical arrow, when, for example the potential illustrated in FIG. 1B, cross the threshold potential the following inverting amplifier switches state. Since this amplifier is not capacitively loaded, it changes state relatively fast, thereby restoring the clock waveshape.
The present invertors have determined that the asymmetrical arrangement of alternately capacitively loaded and non-loaded amplifier stages creates systems problems, which problems arise from the generation of asymmetrical clock pulses, i.e., clock waveforms which do not conform to substantially 50 percent duty cycle.
The first problem that arises results from the fact that the clock waveform asymmetry is cumulative and will tend to limit the number of delay stages that may be cascaded. This may significantly complicate design predictions related to selecting the number of stages required to provide desired phase resolution over a clock period. A second problem that arises is that normally the clock phase selected as an output clock signal, changes periodically due to the phase alignment process. In addition, it is common to utilize both the output clock and its complement in a particular system. In this instance, because of the changes in duty cycle for different clock phases, the relative timing of the transitions of the output clock signal and its complement change, tending to introduce systems timing problems.
The asymmetrical clock pulses occur for the following reasons. Assume that the inverting amplifiers are designed to provide symmetrical waveforms as illustrated in FIG. 1. Nominally the design performance will be valid only over a particular range of for example environmental conditions or device fabrication parameters. If the design constraints are violated or exceeded, the system performance will change. Assume for example that the circuit operating temperature is exceeded resulting in a 50% reduction in rise time exhibited at the output connections of the inverting amplifiers. (Note that an assumed 50% change in rise time is an exaggeration, but is convenient for illustrative purposes.) Normally, parametric changes will be significantly smaller, however, since the effect is cumulative, a small parametric change will significantly alter circuit performance in a circuit having for example 12 or more stages.
Refer to FIGS. 2A-2F which illustrate the effect. These waveforms are presumed to be generated by like circuitry to that generating the waveforms of FIG. 1 except that the amplifier risetimes are reduced by 50 percent (all other parameters remaining the same). Comparing FIGS. 1C and 2C it is seen that due to the faster risetime, switching occurs earlier for the device providing the FIG. 2C waveforms, consequently the negative going transitions of the FIG. 2C waveform occurs before the corresponding negative going transition of the FIG. 1C waveform. The corresponding positive going transitions of the FIG. 1C and 2C waveforms occur at like times. The effect is the relatively negative portion of the 2C waveform is wider than the relatively negative portion of the FIG. 1C waveform, and the relatively positive portion of the FIG. 2C waveform is narrower than that of FIG. 1C. While the waveform of FIG. 1C is symmetrical, the waveform of FIG. 2C is not. As one scans down the waveforms from FIG. 2C representing the output of a second inverting amplifier in the cascade arrangement to FIG. 2F representing the output of a fifth inverting amplifier in the arrangement it is seen that the waveform becomes cumulatively more non-symmetric (compare the times t1 and t2 indicated on the drawing).
The illustrated non-symmetry may occur for a number of reasons including a temperature induced change of risetimes; a temperature induced change in threshold; if the device is fabricated on an integrated circuit using metal-oxide-semiconductor capacitors, a substrate potential induced change of capacitance; to name but a few.